
PIC18F66K80 FAMILY
DS39977F-page 260
 2010-2012 Microchip Technology Inc.
FIGURE 19-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
CCPR5H
CCPR5L
TMR1H
TMR1L
Comparator
Q
S
R
Output
Logic
Special Event Trigger
Set CCP5IF
CCP5 Pin
TRIS
CCP5CON<3:0>
Output Enable
TMR3H
TMR3L
1
0
Compare
4
(Timer1/3 Reset)
Match
Note:
This block diagram uses CCP4 and CCP5, and their appropriate timers as an example. For details on all of
the CCP modules and their timer assignments, see 
Table 19-2.TMR1H
TMR1L
TMR3H
TMR3L
CCPR4H
CCPR4L
Comparator
C4TSEL
Set CCP4IF
1
0
Q
S
R
Output
Logic
Special Event Trigger
CCP4 Pin
TRIS
CCP4CON<3:0>
Output Enable
4
(Timer1/Timer3 Reset)
Compare
Match
C5TSEL